NXP Semiconductors /LPC5410x /VFIFO /FIFOUPDATESPI

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Interpret as FIFOUPDATESPI

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI0RXUPDATESIZE)SPI0RXUPDATESIZE 0 (SPI1RXUPDATESIZE)SPI1RXUPDATESIZE 0RESERVED0 (SPI0TXUPDATESIZE)SPI0TXUPDATESIZE 0 (SPI1TXUPDATESIZE)SPI1TXUPDATESIZE 0RESERVED

Description

SPI FIFO global update register

Fields

SPI0RXUPDATESIZE

Writing 1 updates SPI0 Rx FIFO size to match the SPI0 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed.

SPI1RXUPDATESIZE

Writing 1 updates SPI1 Rx FIFO size to match the SPI1 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed.

RESERVED

Reserved. Read value is undefined, only zero should be written.

SPI0TXUPDATESIZE

Writing 1 updates SPI0 Tx FIFO size to match the SPI0 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed.

SPI1TXUPDATESIZE

Writing 1 updates SPI1 Tx FIFO size to match the SPI1 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed.

RESERVED

Reserved. Read value is undefined, only zero should be written.

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